Add VHDL Support & Newer Verilog Linters (#2229)

* Added VHDL file support with ghdl compiler
* Update ghdl.vim
* Create vcom.vim
* Create xvhdl.vim
* Update xvlog.vim
* Added documentation for VHDL & Verilog linters
* Added tests to VHDL & Verilog linters
This commit is contained in:
John Gentile
2019-01-27 04:46:33 -05:00
committed by w0rp
parent 91c1fc3bb3
commit b8bf7b220d
20 changed files with 569 additions and 4 deletions

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@@ -0,0 +1,19 @@
Before:
call ale#assert#SetUpLinterTest('vhdl', 'ghdl')
After:
unlet! b:command_tail
call ale#assert#TearDownLinterTest()
Execute(The executable should be configurable):
AssertLinter 'ghdl', ale#Escape('ghdl') . ' -s --std=08 %t'
let b:ale_vhdl_ghdl_executable = 'foobar'
AssertLinter 'foobar', ale#Escape('foobar') . ' -s --std=08 %t'
Execute(The options should be configurable):
let b:ale_vhdl_ghdl_options = '--something'
AssertLinter 'ghdl', ale#Escape('ghdl') . ' -s --something %t'

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@@ -0,0 +1,19 @@
Before:
call ale#assert#SetUpLinterTest('vhdl', 'vcom')
After:
unlet! b:command_tail
call ale#assert#TearDownLinterTest()
Execute(The executable should be configurable):
AssertLinter 'vcom', ale#Escape('vcom') . ' -2008 -quiet -lint %t'
let b:ale_vhdl_vcom_executable = 'foobar'
AssertLinter 'foobar', ale#Escape('foobar') . ' -2008 -quiet -lint %t'
Execute(The options should be configurable):
let b:ale_vhdl_vcom_options = '--something'
AssertLinter 'vcom', ale#Escape('vcom') . ' --something %t'

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@@ -0,0 +1,19 @@
Before:
call ale#assert#SetUpLinterTest('verilog', 'vlog')
After:
unlet! b:command_tail
call ale#assert#TearDownLinterTest()
Execute(The executable should be configurable):
AssertLinter 'vlog', ale#Escape('vlog') . ' -quiet -lint %t'
let b:ale_verilog_vlog_executable = 'foobar'
AssertLinter 'foobar', ale#Escape('foobar') . ' -quiet -lint %t'
Execute(The options should be configurable):
let b:ale_verilog_vlog_options = '--something'
AssertLinter 'vlog', ale#Escape('vlog') . ' --something %t'

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@@ -0,0 +1,19 @@
Before:
call ale#assert#SetUpLinterTest('vhdl', 'xvhdl')
After:
unlet! b:command_tail
call ale#assert#TearDownLinterTest()
Execute(The executable should be configurable):
AssertLinter 'xvhdl', ale#Escape('xvhdl') . ' --2008 %t'
let b:ale_vhdl_xvhdl_executable = 'foobar'
AssertLinter 'foobar', ale#Escape('foobar') . ' --2008 %t'
Execute(The options should be configurable):
let b:ale_vhdl_xvhdl_options = '--something'
AssertLinter 'xvhdl', ale#Escape('xvhdl') . ' --something %t'

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@@ -0,0 +1,19 @@
Before:
call ale#assert#SetUpLinterTest('verilog', 'xvlog')
After:
unlet! b:command_tail
call ale#assert#TearDownLinterTest()
Execute(The executable should be configurable):
AssertLinter 'xvlog', ale#Escape('xvlog') . ' %t'
let b:ale_verilog_xvlog_executable = 'foobar'
AssertLinter 'foobar', ale#Escape('foobar') . ' %t'
Execute(The options should be configurable):
let b:ale_verilog_xvlog_options = '--something'
AssertLinter 'xvlog', ale#Escape('xvlog') . ' --something %t'

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@@ -0,0 +1,26 @@
Before:
runtime ale_linters/vhdl/ghdl.vim
After:
call ale#linter#Reset()
Execute(The ghdl handler should parse lines correctly):
AssertEqual
\ [
\ {
\ 'lnum': 41,
\ 'col' : 5,
\ 'type': 'E',
\ 'text': "error: 'begin' is expected instead of 'if'"
\ },
\ {
\ 'lnum': 12,
\ 'col' : 8,
\ 'type': 'E',
\ 'text': ' no declaration for "i0"'
\ },
\ ],
\ ale_linters#vhdl#ghdl#Handle(bufnr(''), [
\ "dff_en.vhd:41:5:error: 'begin' is expected instead of 'if'",
\ '/path/to/file.vhdl:12:8: no declaration for "i0"',
\ ])

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@@ -0,0 +1,36 @@
Before:
runtime ale_linters/vhdl/vcom.vim
After:
call ale#linter#Reset()
Execute(The vcom handler should parse lines correctly):
AssertEqual
\ [
\ {
\ 'lnum': 218,
\ 'type': 'W',
\ 'text': '(vcom-1236) Shared variables must be of a protected type.'
\ },
\ {
\ 'lnum': 73,
\ 'type': 'E',
\ 'text': '(vcom-1136) Unknown identifier "aresetn".'
\ },
\ {
\ 'lnum': 73,
\ 'type': 'E',
\ 'text': 'Bad resolution function (STD_LOGIC) for type (error).'
\ },
\ {
\ 'lnum': 73,
\ 'type': 'E',
\ 'text': 'near ":": (vcom-1576) expecting ";" or ")".'
\ },
\ ],
\ ale_linters#vhdl#vcom#Handle(bufnr(''), [
\ '** Warning: ../path/to/file.vhd(218): (vcom-1236) Shared variables must be of a protected type.',
\ '** Error: tb_file.vhd(73): (vcom-1136) Unknown identifier "aresetn".',
\ '** Error: tb_file.vhd(73): Bad resolution function (STD_LOGIC) for type (error).',
\ '** Error: tb_file.vhd(73): near ":": (vcom-1576) expecting ";" or ")".',
\ ])

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@@ -0,0 +1,24 @@
Before:
runtime ale_linters/verilog/vlog.vim
After:
call ale#linter#Reset()
Execute(The vlog handler should parse lines correctly):
AssertEqual
\ [
\ {
\ 'lnum': 7,
\ 'type': 'W',
\ 'text': '(vlog-2623) Undefined variable: C.'
\ },
\ {
\ 'lnum': 1,
\ 'type': 'E',
\ 'text': '(vlog-13294) Identifier must be declared with a port mode: C.'
\ },
\ ],
\ ale_linters#verilog#vlog#Handle(bufnr(''), [
\ '** Warning: add.v(7): (vlog-2623) Undefined variable: C.',
\ '** Error: file.v(1): (vlog-13294) Identifier must be declared with a port mode: C.',
\ ])

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@@ -0,0 +1,24 @@
Before:
runtime ale_linters/vhdl/xvhdl.vim
After:
call ale#linter#Reset()
Execute(The xvhdl handler should parse lines correctly):
AssertEqual
\ [
\ {
\ 'lnum': 17,
\ 'type': 'E',
\ 'text': '[VRFC 10-91] aresetn is not declared '
\ },
\ {
\ 'lnum': 128,
\ 'type': 'E',
\ 'text': '[VRFC 10-91] m_axis_tx_tdata is not declared '
\ },
\ ],
\ ale_linters#vhdl#xvhdl#Handle(bufnr(''), [
\ 'ERROR: [VRFC 10-91] aresetn is not declared [/path/to/file.vhd:17]',
\ 'ERROR: [VRFC 10-91] m_axis_tx_tdata is not declared [/home/user/tx_data.vhd:128]',
\ ])

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@@ -0,0 +1,18 @@
Before:
runtime ale_linters/verilog/xvlog.vim
After:
call ale#linter#Reset()
Execute(The xvlog handler should parse lines correctly):
AssertEqual
\ [
\ {
\ 'lnum': 5,
\ 'type': 'E',
\ 'text': '[VRFC 10-1412] syntax error near output '
\ },
\ ],
\ ale_linters#verilog#xvlog#Handle(bufnr(''), [
\ 'ERROR: [VRFC 10-1412] syntax error near output [/path/to/file.v:5]',
\ ])

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@@ -61,7 +61,7 @@ Execute(The defaults for the zsh filetype should be correct):
Execute(The defaults for the verilog filetype should be correct):
" This filetype isn't configured with default, so we can test loading all
" available linters with this.
AssertEqual ['iverilog', 'verilator'], GetLinterNames('verilog')
AssertEqual ['iverilog', 'verilator', 'vlog', 'xvlog'], GetLinterNames('verilog')
let g:ale_linters_explicit = 1