Add VHDL Support & Newer Verilog Linters (#2229)

* Added VHDL file support with ghdl compiler
* Update ghdl.vim
* Create vcom.vim
* Create xvhdl.vim
* Update xvlog.vim
* Added documentation for VHDL & Verilog linters
* Added tests to VHDL & Verilog linters

test/handler/test_ghdl_handler.vader

@@ -0,0 +1,26 @@
+Before:
+  runtime ale_linters/vhdl/ghdl.vim
+
+After:
+  call ale#linter#Reset()
+
+Execute(The ghdl handler should parse lines correctly):
+  AssertEqual
+  \ [
+  \   {
+  \     'lnum': 41,
+  \     'col' : 5,
+  \     'type': 'E',
+  \     'text': "error: 'begin' is expected instead of 'if'"
+  \   },
+  \   {
+  \     'lnum': 12,
+  \     'col' : 8,
+  \     'type': 'E',
+  \     'text': ' no declaration for "i0"'
+  \   },
+  \ ],
+  \ ale_linters#vhdl#ghdl#Handle(bufnr(''), [
+  \   "dff_en.vhd:41:5:error: 'begin' is expected instead of 'if'",
+  \   '/path/to/file.vhdl:12:8: no declaration for "i0"',
+  \ ])