Add VHDL Support & Newer Verilog Linters (#2229)

* Added VHDL file support with ghdl compiler
* Update ghdl.vim
* Create vcom.vim
* Create xvhdl.vim
* Update xvlog.vim
* Added documentation for VHDL & Verilog linters
* Added tests to VHDL & Verilog linters
This commit is contained in:
John Gentile
2019-01-27 04:46:33 -05:00
committed by w0rp
parent 91c1fc3bb3
commit b8bf7b220d
20 changed files with 569 additions and 4 deletions

View File

@@ -0,0 +1,24 @@
Before:
runtime ale_linters/verilog/vlog.vim
After:
call ale#linter#Reset()
Execute(The vlog handler should parse lines correctly):
AssertEqual
\ [
\ {
\ 'lnum': 7,
\ 'type': 'W',
\ 'text': '(vlog-2623) Undefined variable: C.'
\ },
\ {
\ 'lnum': 1,
\ 'type': 'E',
\ 'text': '(vlog-13294) Identifier must be declared with a port mode: C.'
\ },
\ ],
\ ale_linters#verilog#vlog#Handle(bufnr(''), [
\ '** Warning: add.v(7): (vlog-2623) Undefined variable: C.',
\ '** Error: file.v(1): (vlog-13294) Identifier must be declared with a port mode: C.',
\ ])