Add VHDL Support & Newer Verilog Linters (#2229)

* Added VHDL file support with ghdl compiler
* Update ghdl.vim
* Create vcom.vim
* Create xvhdl.vim
* Update xvlog.vim
* Added documentation for VHDL & Verilog linters
* Added tests to VHDL & Verilog linters
This commit is contained in:
John Gentile
2019-01-27 04:46:33 -05:00
committed by w0rp
parent 91c1fc3bb3
commit b8bf7b220d
20 changed files with 569 additions and 4 deletions

View File

@@ -0,0 +1,18 @@
Before:
runtime ale_linters/verilog/xvlog.vim
After:
call ale#linter#Reset()
Execute(The xvlog handler should parse lines correctly):
AssertEqual
\ [
\ {
\ 'lnum': 5,
\ 'type': 'E',
\ 'text': '[VRFC 10-1412] syntax error near output '
\ },
\ ],
\ ale_linters#verilog#xvlog#Handle(bufnr(''), [
\ 'ERROR: [VRFC 10-1412] syntax error near output [/path/to/file.v:5]',
\ ])