mirror of
https://github.com/dense-analysis/ale.git
synced 2026-01-09 04:52:29 +08:00
Add VHDL Support & Newer Verilog Linters (#2229)
* Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
This commit is contained in:
18
test/handler/test_xvlog_handler.vader
Normal file
18
test/handler/test_xvlog_handler.vader
Normal file
@@ -0,0 +1,18 @@
|
||||
Before:
|
||||
runtime ale_linters/verilog/xvlog.vim
|
||||
|
||||
After:
|
||||
call ale#linter#Reset()
|
||||
|
||||
Execute(The xvlog handler should parse lines correctly):
|
||||
AssertEqual
|
||||
\ [
|
||||
\ {
|
||||
\ 'lnum': 5,
|
||||
\ 'type': 'E',
|
||||
\ 'text': '[VRFC 10-1412] syntax error near output '
|
||||
\ },
|
||||
\ ],
|
||||
\ ale_linters#verilog#xvlog#Handle(bufnr(''), [
|
||||
\ 'ERROR: [VRFC 10-1412] syntax error near output [/path/to/file.v:5]',
|
||||
\ ])
|
||||
Reference in New Issue
Block a user