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Add iverilog for verilog (#63)

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* Add iverilog for verilog

* Remove extra spacing/blank line

* Set column to 1
This commit is contained in:
Masahiro H
2016-10-08 20:29:45 +09:00
committed by w0rp
parent 197137aea0
commit bd6da4489d
3 changed files with 50 additions and 0 deletions
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@@ -46,6 +46,7 @@ name. That seems to be the fairest way to arrange this table.
| SCSS | [sass-lint](https://www.npmjs.com/package/sass-lint), [scss-lint](https://github.com/brigade/scss-lint) |
| Scala | [scalac](http://scala-lang.org) |
| TypeScript | [tslint](https://github.com/palantir/tslint) |
| Verilog | [iverilog](https://github.com/steveicarus/iverilog) |
| Vim | [vint](https://github.com/Kuniwak/vint) |
| YAML | [yamllint](https://yamllint.readthedocs.io/) |