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Add iverilog for verilog (#63)

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* Add iverilog for verilog

* Remove extra spacing/blank line

* Set column to 1
This commit is contained in:
Masahiro H
2016-10-08 20:29:45 +09:00
committed by w0rp
parent 197137aea0
commit bd6da4489d
3 changed files with 50 additions and 0 deletions
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doc/ale.txt
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@@ -59,6 +59,7 @@ The following languages and tools are supported.
* SCSS: 'sasslint', 'scsslint'
* Scala: 'scalac'
* TypeScript: 'tslint'
* Verilog: 'iverilog'
* Vim: 'vint'
* YAML: 'yamllint'