Add Yosys linter for Verilog files. (#3713)

* Add yosys for verilog files.

* Add handler test for yosys.

* fix typo in yosys handler test

* fix array order in yosys handler test

* add yosys linter to filetype defaults test

* fix duplicate tag

* add 'yosys' to 'ale-supported-languages-and-tools.txt'

supported-tools.md

@@ -559,6 +559,7 @@ formatting.
   * [verilator](http://www.veripool.org/projects/verilator/wiki/Intro)
   * [vlog](https://www.mentor.com/products/fv/questa/)
   * [xvlog](https://www.xilinx.com/products/design-tools/vivado.html)
+  * [yosys](http://www.clifford.at/yosys/)
 * VHDL
   * [ghdl](https://github.com/ghdl/ghdl)
   * [vcom](https://www.mentor.com/products/fv/questa/)