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Use equal signs for language documentation sections

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w0rp
2017-07-08 14:17:26 +01:00
parent f9aa7d3b9a
commit fdc7166c3c
40 changed files with 116 additions and 116 deletions
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doc/ale-verilog.txt
+4 -4
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@@ -2,7 +2,7 @@
ALE Verilog/SystemVerilog Integration *ale-verilog-options*
-------------------------------------------------------------------------------
===============================================================================
ALE can use two different linters for Verilog HDL:
iverilog:
@@ -20,13 +20,13 @@ defining 'g:ale_linters' variable:
\ let g:ale_linters = {'systemverilog' : ['verilator'],}
<
-------------------------------------------------------------------------------
===============================================================================
iverilog *ale-verilog-iverilog*
No additional options
-------------------------------------------------------------------------------
===============================================================================
verilator *ale-verilog-verilator*
g:ale_verilog_verilator_options *g:ale_verilog_verilator_options*
@@ -39,5 +39,5 @@ g:ale_verilog_verilator_options *g:ale_verilog_verilator_options*
For example `'-sv --default-language "1800-2012"'` if you want to enable
SystemVerilog parsing and select the 2012 version of the language.
-------------------------------------------------------------------------------
===============================================================================
vim:tw=78:ts=2:sts=2:sw=2:ft=help:norl: