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In the vein of commit ea72d66b "Verilator current file search path (#3500)"
This includes the directory of the current file in the library
search path. From `man iverilog`:
-ylibdir
Append the directory to the library module search
path. When the compiler finds an undefined module, it
looks in these directories for files with the right name.
45 lines
1.4 KiB
VimL
45 lines
1.4 KiB
VimL
" Author: Masahiro H https://github.com/mshr-h
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" Description: iverilog for verilog files
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call ale#Set('verilog_iverilog_options', '')
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function! ale_linters#verilog#iverilog#GetCommand(buffer) abort
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return 'iverilog -t null -Wall '
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\ . '-y%s:h '
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\ . ale#Var(a:buffer, 'verilog_iverilog_options')
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\ . ' %t'
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endfunction
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function! ale_linters#verilog#iverilog#Handle(buffer, lines) abort
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" Look for lines like the following.
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"
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" tb_me_top.v:37: warning: Instantiating module me_top with dangling input port 1 (rst_n) floating.
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" tb_me_top.v:17: syntax error
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" memory_single_port.v:2: syntax error
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" tb_me_top.v:17: error: Invalid module instantiation
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let l:pattern = '^[^:]\+:\(\d\+\): \(warning\|error\|syntax error\)\(: \(.\+\)\)\?'
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let l:output = []
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for l:match in ale#util#GetMatches(a:lines, l:pattern)
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let l:line = l:match[1] + 0
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let l:type = l:match[2] =~# 'error' ? 'E' : 'W'
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let l:text = l:match[2] is# 'syntax error' ? 'syntax error' : l:match[4]
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call add(l:output, {
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\ 'lnum': l:line,
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\ 'text': l:text,
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\ 'type': l:type,
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\})
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endfor
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return l:output
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endfunction
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call ale#linter#Define('verilog', {
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\ 'name': 'iverilog',
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\ 'output_stream': 'stderr',
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\ 'executable': 'iverilog',
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\ 'command': function('ale_linters#verilog#iverilog#GetCommand'),
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\ 'callback': 'ale_linters#verilog#iverilog#Handle',
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\})
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